Digital Phase Locked Loop (DPLL) circuits may be used to generate system clocks. The DPLL may generate a system clock based on a reference input clock. When the DPLL loses the reference input clock during operation, the DPLL operates in a holdover event. Certain systems may require their system clock to perform accurately even in the holdover events. The holdover frequency accuracy may be defined in terms of a maximum fractional frequency offset and drift over a period of time.
Analog Devices Inc., the assignee of the present invention, manufactures integrated circuits that include a direct digital synthesizer (DDS) and a digital-to-analog converter (DAC) to implement a digitally-controlled oscillator within a DPLL. A digital control word may tune the DDS to generate a digital clock which is converted into an analog sine wave by the DAC. However, the DDS+DAC implementation requires a filter for removing harmonics at the DAC output. The filter cannot easily be fabricated within the integrated circuit in which the DPLL is fabricated, and therefore, it is provided as an external component, which increases cost and complexity of the clock system. Additionally, the DDS+DAC design requires a comparator for converting the sine waves to square waves so that the square waves can be used as a system clock. These extra components occupy additional space and increase cost.
Therefore, there is a need for a highly stable and high performance clock system that is persistent and accurate during holdover events, but consumes less power and costs less.